1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, relates to a chip size (scale) package (hereinafter referred to as “CSP”) structure having a multiple layer wiring structure.
This application is counterpart of Japanese patent applications, Serial Number 333404/2002, filed Nov. 18, 2002, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In a semiconductor device of this type, first wiring layer formed with wiring patterns is formed, via an insulating layer, on a semiconductor substrate formed with an integrated circuit, and second wiring layer formed with wiring patterns are further formed thereon via an insulating layer. I/O pads of the integrated circuit and the first wiring layer, and the first wiring layer and the second wiring layer are electrically connected to each other through via holes formed in the respective insulating layers, depending on requirement.
Bump electrodes (this electrode is also referred to as post electrode or columnar-shaped electrode or pillar-shaped electrode) are formed so as to erect from the uppermost layer wiring (the second layer wiring in this case), and external electrodes to be electrically connected to an external circuit board (this board is also referred to as mother board or wiring substrate) are formed at top surface of the bump electrodes, respectively. Further, a sealing resin layer is formed to cover the uppermost layer wiring and side surfaces of the bump electrodes (e.g. see Patent Literature 1).
[Patent Literature 1]
JP-A-2002-93945
In case of the semiconductor device having the CSP structure, the external electrodes formed on the top surface of the bump electrodes are electrically connected and fixed to the external circuit board through solder reflow or the like. That is, the semiconductor device is mounted on the external circuit board.
With this mounting arrangement, a thermal stress caused by a difference in thermal expansion coefficient between the semiconductor device and the external circuit board is absorbed by plastic deformation of the bump electrodes. As a result, breakage due to thermal fatigue in connecting portions between the external circuit board and the external electrodes, or physical influence of the thermal stress from wiring paths inside the CSP structure to the integrated circuit can be suppressed. Accordingly, as the height (the height means that distance between the top surface and the bottom surface) of the bump electrode increases, its plastic deformation is facilitated so that the suppression effect against the influence of the thermal stress is enhanced.
However, since each of the bump electrodes is erected from the uppermost layer wiring as described above, it is impossible to make the bump electrode longer without changing the thickness of the whole semiconductor device. Further, there has been a problem that for reducing the thickness of the whole semiconductor device or increasing the number of layers of the wiring of the CSP structure without changing the thickness thereof, the height of the bump electrode should be shortened contrariwise.